1. Technical Field
The present invention relates in general to circuit interconnects (nets) and in particular to a method for efficient routing of nets of a circuit. Still more particularly, the present invention relates to a method and program product for estimating and subsequently reducing coupled noise in nets during preliminary design (i.e., global routing) of a circuit.
2. Description of the Related Art
One cause of propagation delays or faults in interconnects (or nets) of Very Large-Scale Integration (VLSI) circuits is noise induced by capacitive coupling of neighboring nets. Because of the lack of a dedicated ground plane and poor shielding, VLSI interconnects can have severe coupling problems, which ultimately reduces the efficiency of signal propagation in the circuit and in extreme cases causes operation of the circuit to fail. Presently, most of the problems caused by coupling are avoided by conservative design practices such as buffering long interconnect lines and utilizing restoring logic circuits, etc.
Ideally, the capacitive-coupling problem can be eliminated with a more accurate pre-layout noise analysis. However, there is generally a lack of information about wire couplings, and most coupling problems can only be identified after the circuit design is fully constructed, i.e., after routing of the interconnects. The process of actually routing the interconnects is referred to as detailed routing. Following detailed routing, both a detailed interconnect extraction of the signal couplings and a circuit simulation are required to identify coupling problems and assess the severity of the problems.
Typically, after detailed routing, a resistive-capacitive (RC) representation for each net is extracted from the layout, including coupling capacitances. Then, the coupling capacitances are examined to determine neighboring nets that can couple noise to the net under consideration. The net under consideration is called a xe2x80x9cvictimxe2x80x9d net, and the neighboring nets are called xe2x80x9caggressorxe2x80x9d nets. Each aggressor net""s coupling is then simulated. Typically, the process requires knowledge of the transition time of the aggressor net. In most cases, only the largest aggressor capacitive couplings are examined. The noise contributed by each of these aggressor nets is then aggregated using information about the time (or time window) when signals propagating on the aggressor nets switch. The resulting total noise is compared to the noise immunity of each receiver of the victim net, and if the total noise exceeds the noise immunity, the net is deemed to have a noise failure.
Thus, in order to conduct such a noise analysis, the number of aggressors, the strength of the couplings, and the switching characteristics of the aggressors must all be known.
Fixing the coupling problems after the detailed routing requires at least a new routing and another extraction and noise verification. Since the noise-analysis and subsequent adjustments occur late in the design cycle, the noise analysis and correction has a severe impact on the product release schedule.
Thus, methods are required to assess potential coupling noise problems early in the design cycle. The task is very difficult since the data needed for noise analysis is only available very late in the design cycle. Hence, most designers resort to a worst case analysis. Under the worst case analysis, each wire (net) is assumed to be coupled to wires on either side at the minimum permissible spacing. Accordingly, the wire length is constrained such that it does not exceed a threshold length where the worst-case coupling may disturb any of the receivers connected to the net. Under the analysis, the maximum wire length is usually very pessimistic for of most nets because of the conservative coupling assumption. Also, to keep wire length below the maximum wire length, buffers are inserted periodically in the net, and the driver size may be increased (a larger driver will have a longer wire threshold length). Both of the above actions result in higher power consumption and may also have an adverse effect on chip timing.
Traditionally, the worst-case model is utilized to make all decisions (spacing, shielding, buffering) and leads to quite a few post-design fails. Use of the worst-case model leads to significant over-design, because a lot of nets which would not have noise problems after layout are constrained through buffering or shielding.
The present invention recognizes that it would be desirable to have a method and system for efficiently evaluating coupling noise for interconnects during the global routing stage of circuit design. The invention further recognizes that a method and system by which and major noise-induced failures are avoided early in the circuit design (i.e., prior to detailed routing) would be a significant improvement. These and other benefits are provided by the invention described herein.
Disclosed is a method for pre-design estimation of coupling noise and avoidance of coupling noise failures in interconnects. An initial routing of a plurality of nets is estimated utilizing global paths. Then, the worst-case and average-case models for various parameters of each net are evaluated. With these models, a noise analysis is completed by which a determination is made whether coupling noise of any one of the nets is above a threshold level for noise-induced failure (i.e., a noise-failure threshold). When it is determined that the estimated coupling noise of a net falls below the noise-failure threshold, a response mechanism is triggered for later implementation during detailed routing of the nets to prevent the coupling noise from reaching the noise-failure threshold.
In the preferred embodiment, the nets"" parameters utilized in the noise analysis include aggressor capacitance, drive strength of aggressor, transmission times, and switching windows. Responses to the evaluation includes increased spacing between nets and utilization of wires adjacent to non-switching lines, such as power lines, for routing the nets.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.